The SoC Development team is looking for a recent college graduate to join a team of experienced engineers working on verification of the Host interface for HDD and SSD SoCs. The Host interface IP consists of SAS and SATA high speed serial protocols.
ESSENTIAL DUTIES AND RESPONSIBILITIES:
* Develop UVM testbenches for SoC level and block level verification of the Host interface * Testplan documentation and code reviews * Verify various features using targeted/random/corner-case/coverage tests * Simulate and debug RTL and digital circuits using tools such as Cadence Incisive, Mentor Graphic QuestaSim, and/or Synopsys VCS * Regression management and code/functional coverage analysis
* Recent college graduate with a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. * Minimum of 3.0 GPA * Exceptional written and verbal communication skills * Strong technical skills in area of study * Interest in ASICs, SoCs, HDD, flash, semiconductor components * Proficient in Microsoft Office applications * Strong team-player who can collaborate with colleagues
DESIRED SKILLS AND KNOWLEDGE:
* Verification methodology - UVM * System Verilog, Verilog * Object Oriented Programming * Linux operating system * High Speed Serial Interface Protocols - SAS, SATA, PCIe * ARM AMBA - APB, AHB, AXI
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